1. The Field of the Invention
This invention relates to semiconductor devices, especially integrated semiconductor devices, and to methods of manufacturing such devices.
2. Description of the Related Art
Junction Isolated smart power technologies have the drawback of large lateral isolation structures, the area consumed by such structures being dependent on the required blocking voltage. The higher the voltage requirement, the more area needed. Vertical isolation is typically achieved by using highly doped implanted buried layers, requiring large thermal budgets.
Technologies processed on SOI (Silicon on Insulator) use trench isolation, guaranteeing both lateral and vertical isolation through oxide layers. However, SOI is still expensive. Moreover, it has some inherent drawbacks for power switching and high voltage applications: (1) in order to reduce the effect of the back-gate effect (substrate potential), the buried oxide needs to be thick, (2) a thick oxide poses a barrier to the heat generated in a power switch due to the much lower thermal diffusivity in oxide compared to silicon. Hence, the devices will be much more prone to thermal destruction upon power switching, and have to be designed accordingly.
A good compromise is to use deep trench isolation on a junction isolated technology. This way, the high packing density of trench structures can be combined with the good thermal properties of bulk silicon.
U.S. Pat. No. 4,140,558: B. T. Murphy et al., Isolation of Integrated Circuits Utilizing Selective Etching and Diffusion, Feb. 20, 1979 shows an early example of isolation.
U.S. Pat. No. 5,914,523: R. Bashir et al., “Semiconductor Device Trench Isolation Structure with Polysilicon Bias Contact”, Jun. 22, 1999 shows a trench isolation structure which includes a field oxide (FOX) layer on the surface of the semiconductor substrate and an isolation trench which extends vertically through the FOX layer and into the semiconductor substrate. Because of this structural arrangement of the isolation trench, the isolation trench has both semiconductor substrate sidewalls and FOX sidewalls.
U.S. Pat. No. 6,362,064: J. M. McGregor et al., “Elimination of Walk-Out in High Voltage Trench Isolated Devices”, Mar. 26, 2002 shows another example of trench isolation.
F. De Pestel et al., “Development of a Robust 50V 0.35 μm Based Smart Power Technology Using Trench Isolation”, ISPSD 2003, pp182-185 again shows a single trench.
V. Parthasarathy et al., “A Multi-Trench Analog+Logic Protection (M-Trap) for Substrate Cross-talk Prevention in a 0.25 μm Smart Power Platform with 100V High-Side Capability”, ISPSD, pp 427-430 (2004) shows an example having multiple trenches.